Conventional approaches to generating quadrature clocks generally require at least four delay stages in the ring. A four-stage oscillator runs at approximately half the speed as a two-stage one. As such, one shortcoming to conventional approaches is that in order to increase the speed for a four-stage oscillator, more power must be expended. Conventional approaches to generating quadrature clocks also generally require more area on silicon to implement. One approach to generating quadrature clocks using a two-stage approach is described by Anand (“A CMOS Clock Recovery Circuit for 2.5 Gb/s NRZ data,” IEEE Journal of Solid-State Circuits, March 2001, pp. 432-439). Anand teaches a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase shift technique.
However, one shortcoming with this approach is that the circuit has very little gain-margin. Hence, its manufacturability is questionable. Exemplary embodiments of the two-stage ring oscillator described herein address this shortcoming by providing a delay stage with local positive feedback that causes the output to grow exponentially with time. In this respect, embodiments described herein provide for a robust design that is highly manufacturable.
Other conventional approaches to generating clocks seek to set the free running frequency as close as possible to the desired value across all process and temperature variations. One such approach is taught by Wilson, et al. (“A CMOS Self-Calibrating Frequency Synthesizer,” IEEE Journal of Solid-State Circuits, Oct. 200, pp. 1437-1444). Wilson, et al. teaches a programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described.
Wilson, et al. teaches that in fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies and cover the desired range of the synthesizer output frequencies for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain Ko large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. Wilson, et al. further teaches that the wide tuning range is realized by digital control, with process variability managed through self-calibration. However, while the approach taught by Wilson, et al. apparently addresses process variations, Wilson, et al. apparently fails to compensate for temperature changes.
A master-slave PLL scheme is proposed by Wadhwa, et al. (“A low-power 0.13 μm CMOS OC-48 SONET and XAUI compliant SERDES,” IEEE Custom Integrated Circuits Conference, September 2003, pp. 577-580). Wadhwa, et al. teaches a continuous rate octal 1.0 to 3.2 Gb/s serializer/deserializer circuit that meets SONET and XAUI requirements. Wadhwa et al. teaches that the performance of the SERDES surpasses stringent OC-48 jitter generation and tolerance specifications and teaches that this is achieved with the use of a master-slave PLL tuning scheme and meticulous attention to layout and isolation techniques. Implemented in a 0.13 μm digital CMOS technology, the part exhibits less than 5 mUI r.m.s. jitter and the 1.2 mm2 transceiver dissipates 160 mW. While Wadhwa, et al. appears to address both process and temperature variations continuously, one shortcoming to this approach, however, is that extra area is required by the master PLL.